Invited Speakers
JOINT KEYNOTE SPEAKERS
The Future of Short Reach Interconnect: A Technology Perspective
Plenary Auditorium
Tuesday September 20, 2022 (09:20 - 10:00)
Chair: Andrea Baschirotto
The unprecedented information explosion and its exponentially increasing demands on data traffic and processing are pushing a rapid and diverse evolution in short reach interconnect technologies. In the background of this race, CMOS technology is not providing the usual node over node boost in performance to help SerDes designers cope with higher bandwidth and data rates. Breakthroughs in high speed electrical interconnect and new approaches in optical interconnect, such SiPho, NPO (near package optics) and CPO (co-packaged optics) promise improved performance, energy efficiency and density. How we re-define “Short Reach Interconnect” and how are these new technologies going to address the ever more complex power and density problems facing our industry? What are the specific challenges that new and emerging applications such as AI and HPC are posing on interconnect? How interconnect technologies are going to respond to the need for die disaggregation and multi-die IC products? Is a Chiplet IC ecosystem around the corner?
Davide Tonietto (Huawei Technologies, CA)
Davide Tonietto is Huawei Fellow and Senior Director of Hisilicon Serial Link Team (HiLink) a global organization with teams in Canada and China. Since 2011 he is responsible for the SerDes IP technology roadmap definition, execution and integration within Hisilicon high performance ASICs product lines. Over the past decade his organization provided SerDes for over 200 high performance ASICs utilized in a wide variety of Huawei products ranging from Networking, DC, HPC, Wireless infrastructure and Mobile applications.
Davide received the Laurea Degree in Electrical Engineering from Pavia University, Italy in 1996. He has worked in several IC companies as analog designer and technical manager. He holds more than 20 US patents in the areas of Analog and Mixed Signal IC design and wireline communication systems and authored several papers on the subjects. His current research interests are in the area of SerDes architecture, design, optimization, testing and reliability for 100Gbps and beyond for both copper and optical applications.
Semiconductors Take the Driver’s Seat - Challenges and Opportunities for the Car of the Future
Plenary Auditorium
Tuesday September 20, 2022 (10:00 - 10:40)
Chair: Davide Giacomini
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90% of the innovations in modern vehicles are enabled by semiconductors. The trend towards autonomous driving and electrification of drive train poses a lot of additional requirements on electronics in the vehicle, which cannot be met by using semiconductor components from the consumer domains. The talk will illustrate the main challenges on semiconductor devices in automotive use cases related to computing performance, power consumption, reliability, sensor accuracy and robustness, security and functional safety for enabling the vehicle of tomorrow. We will provide an outlook on advanced semiconductor technologies and concepts which will be instrumental to tackle these challenges successfully.
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Tim Gutheit (Infineon Technologies, DE)
Tim Gutheit is Vice President of Technology & Innovation of Infineon’s Automotive Division. He is responsible for the innovation and predevelopment strategy of that division, which includes roadmaps for technology and development methodologies, the global development center footprint and competence development of the R&D staff. From 2008 to 2011 Tim Gutheit was leading the development group for Automotive Power Semiconductor Platforms, in which wafer and package technologies and design kits for automotive power ICs and discrets are set up. From 2005 to 2008 he headed Infineon’s product line for high integration IC in automotive powertrain and safety applications. Tim Gutheit started his career 1992 at Daimler Benz’ central research lab in Ulm, working on materials for high temperature electronics before moving on to Siemens Semiconductor (later Infineon Technologies) where he held numerous management positions in R&D and Operations. Until December 2019 Tim Gutheit was member of the advisory board of VDE, the German Association for Electrical, Electronic & Information Technologies, and head of board of the technical society GMM, the VDE/VDI Society of Microelectronics, Microsystems and Precision Engineering. He is also active in the “PLS - Plattform Lernende Systeme – Platform For Artificial Intelligence” and is member of the “Council on technological sovereignty” of the German Ministry for Education & Research BMBF. Tim Gutheit has earned a diploma and a Ph.D. in physics of the Technical University in Munich, Germany, and holds 12 patents.
Integrated Circuits as Key Enabler for Today’s Smart MEMS Sensors
Plenary Auditorium
Wednesday September 21, 2022 (08:30 - 09:10)
Chair: Renato Lombardi
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The requirements and capabilities of smart MEMS sensors are constantly increasing. As a consequence, the challenges in development of the ASICs driving this progress increased significantly over the years. Many fields have to come together to enable this: ranging from high-precision analog mixed signal circuitry to support the ultimate goal of an “ideal” sensor transfer function with no deviation with environmental changes up to power-optimized digital logic with customized microcontrollers. Embedded software is classifying signals, correcting errors and fusioning data from different domains while new process technologies are introduced, package sizes are reduced and 3D integration is established.
To gain some comprehensive overview of these new challenges on ASIC development, in the first sequence of the talk new smart MEMS sensor modules and market requirements will be elaborated. In the second sequence an insight about continuing optimization of performance for signal conditioning of physical and chemical sensors with respect to high signal to noise ratio, offset stability and linearity while still continuously lowering power consumption will be given. In the third sequence the concurrent increase of digital capability from edge-AI supporting structures to reduce of all power consumption of meshed sensors up to new security features for trusted domains of IoT connected devices will be discussed and in the fourth sequence, the demands on packaging size and impacts on 3D integration concept will be presented.
Markus Ulm (Bosch Sensortec, DE)
Dr. Markus Ulm is Chief Technical Officer of Bosch Sensortec. He is responsible for research and development of sensors based on microelectromechanical systems (MEMS) for consumer electronics and related industries. Markus has a Master degree in Physics from the University of Oregon and a Diploma Degree in Physics from the Karlsruhe Institute of Technology. He continued his studies in the field of MEMS and graduated from the University of Stuttgart with a Dr. Ing. degree in Semiconductor Technology in 2003. During his career he held various positions in the field of MEMS, semiconductors and sensor research and development in the Bosch Group, such as Section Manager in the Bosch Research and Technology Center North America, Section Manager for Automotive Gyroscopes and IMUs, Director of Sensor Predevelopment as well as VP for Consumer Sensor Product Development.
The Next “Automation Age”: How Semiconductor Technologies Are Changing Industrial Systems and Applications
Plenary Auditorium
Wednesday September 21, 2022 (11:10 - 11:50)
Chair: Davide Pandini
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Radical transformation is remaking the industrial world to be more sophisticated and sustainable: the next “Automation Age.” The changes are driven by demand for enhanced safety for people and equipment in the factories, higher levels of intelligence in processes, and greater flexibility and efficiency.
Newer semiconductor technologies like wide-bandgap silicon carbide and gallium nitride, combined with advanced digital control architectures, can deliver significantly higher power densities and conversion efficiencies than conventional silicon technologies.
Advances in smart power BCD process technologies, with embedded phase-change memories, can facilitate transitions from analog to digital control improving motor-control and factory-automation applications. Embedded on-chip, galvanic isolation extends or supersedes earlier-generation system-level protections with superior intrinsic safety and robustness. At the same time, it protects the user from electric shock while delivering exceptional power and high-speed data transfer across isolated barriers.
These are just some of the innovations emerging from an industrial electronics sector striving to meet the smart industry trends of the current and foreseeable future.
Domenico Arrigo (STMicroelectronics, IT)
Domenico Arrigo is General Manager for the Industrial & Power Conversion Division at STMicroelectronics, based in Milan, Italy, since 2016. He has 26 years of experience in Industrial, including advanced System-on-Chip solutions for motor control, energy management, factory automation and industrial connectivity. He is the author of several international papers and patents in the industrial field and his professional experience was the subject of an Industry 4.0 essay book. He is currently a member of the Board of Directors of a few Industrial Associations as Meters&More AISBL and Prime Alliance. Domenico Arrigo was born in Palermo, Italy, in 1969, and graduated from Palermo University in Electrical Engineering.
ESSDERC KEYNOTE SPEAKERS
IBM Quantum Computing Technology
Plenary Auditorium
Tuesday September 20, 2022 (16:40 - 17:20)
Chair: TBA
Quantum computing systems are built from the bottom up reaching the limits of what can be classically simulated. The IBM Quantum Development Roadmap describes our vision of creating a quantum computing ecosystem delivering quantum applications through the cloud. This requires developing the entire quantum computing stack starting from the qubit and quantum processor technology, control electronics to software, algorithms and applications for quantum computing, implemented in the cloud and integrated with high performance computing. We describe the recent development of our quantum computing systems and the scientific advances that enabled scaling superconducting quantum processors to 127 qubits. Besides scale, also quality and speed will be discussed building the key metric for measuring the performance of quantum computation.
Heike Riel (IBM Research Europe, CH)
Dr. Heike Riel is IBM Fellow, Head of Science & Technology and Lead of IBM Research Quantum Europe & Africa. She leads the research agenda and operation of the Science & Technology department aiming to create scientific and technological breakthroughs in Quantum Computing and Technologies, Physics of Artificial Intelligence, Nanoscience and Nanotechnology and to explore new directions to computing. She is a distinguished expert in semiconductor electronic and optoelectronic devices, nanotechnology and nanosciences and focuses her research on advancing the frontiers of information technology through the physical sciences.
She received the master’s in physics from the Friedrich-Alexander University of Erlangen-Nürnberg and the PhD in physics from University of Bayreuth and an MBA from Henley Business College (UK). She has authored more than 150 peer-reviewed publications and filed more than 50 patents
She has received several prestigious honors, e.g., elected member of the Leopoldina – German National Academy of Sciences and the Swiss Academy of Engineering Sciences; she was awarded the APS David Adler Lectureship Award in the Field of Materials Physics, the Applied Physics Award of the Swiss Physical Society, and the 2022 IEEE Andrew S. Grove Award. She was honored as Fellow of the American Physical Society, and with an honorary doctorate by Lund University.
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SIC Power Device Mass Commercialization
Plenary Auditorium
Wednesday September 21, 2022 (14:20 - 15:00)
Chair: Piero Malcovati
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Silicon (Si) power devices have dominated power electronics due to their excellent starting material quality, ease of fabrication, low cost volume production, and proven reliability. Although Si power devices continue to make progress, they are approaching their operational limits primarily due to their relatively low bandgap and critical electric field that result in high conduction and switching losses, and poor high temperature performance.
In this keynote, the favorable material properties of Silicon Carbide (SiC), which allow for highly efficient power devices with reduced form-factor and cooling requirements, will be outlined. High impact application opportunities, where SiC devices are displacing their incumbent Si counterparts, will be reported. Material and device fabrication aspects will be highlighted with an emphasis on the processes that do not carry over from the mature Si manufacturing world and are thus specific to SiC. Fab models will be analyzed, and the vibrant U.S. SiC manufacturing infrastructure (that mirrors that of Si) will be presented. Barriers to SiC mass commercialization will be identified and discussed. These include the higher than silicon device cost, reliability and ruggedness concerns, defects that degrade device performance, and the need for a trained workforce to skillfully insert SiC into power electronics systems.
Victor Veliadis (PowerAmerica/North Carolina State University, US)
Dr. Victor Veliadis is Executive Director and CTO of PowerAmerica, a WBG semiconductor power electronics consortium. At PowerAmerica, he has managed a budget of $146 million that he strategically allocated to 200 industrial and University projects to accelerate WBG semiconductor clean energy manufacturing, workforce development, and job creation. His PowerAmerica educational activities have trained 410 University FTE students in applied WBG projects, and engaged 4100 attendees in tutorials, short courses, and webinars.
Dr. Veliadis is an ECE Professor at NCSU and an IEEE Fellow and EDS Distinguished Lecturer. He has 27 issued U.S. patents, 6 book chapters, and over 125 peer-reviewed publications. Prior to entering academia and taking an executive position at Power America in 2016, Dr. Veliadis spent 21 years in the semiconductor industry where his work included design, fabrication, and testing of SiC devices, GaN devices for military radar amplifiers, and financial and operations management of a commercial semiconductor fab. He has a Ph.D. degree in Electrical Engineering from John Hopkins University (1995).
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On the Scaling Potential of Transistors with Low Dimensional Materials
Plenary Auditorium
Thursday September 22, 2022 (08:30 - 09:10)
Chair: Francesco Maria Puglisi
Low dimensional materials, carbon nanotubes and transition metal dichalcogenides, hold promise for continued transistor scaling. Over the past decade, large progress has been made to improve the quality of the channel materials, to reduce contact resistance and scale gate dielectric. In spite of the progress, full demonstration of potential is missing. In this talk, we will describe current state of the art for transistors with these materials and detail challenges that need to be solved before technological adoption would come other consideration. We will discuss their scaling potential and describe our work to enable it.
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Iuliana Radu (TSMC, TW)
Iuliana Radu has joined TSMC Taiwan in Oct 2021 to lead exploratory devices activities in Corporate Research. Prior to that, she has established imec's Beyond CMOS and Quantum Computing programs. Her activities in classical devices include work on transistors with 2D materials, spintronics based concepts for logic applications, wave computing and Si CMOS at cryogenic temperatures. The work on quantum computing targeted building better qubits with superconducting circuits and electron spin in Si.
Iuliana has received a PhD in Physics from MIT in 2009 where she searched for Majorana fermions in the quest to build very reliable qubits for Quantum Computing. She has been an author on over 200 papers in leading peer-reviewed journals and conferences. She has given more than 50 invited talks at international conferences and seminars where she is a frequent speaker on quantum computing and exploratory devices for classical computing.
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ESSCIRC KEYNOTE SPEAKERS​
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Reminiscing through 40 Years of CMOS Analog Circuit Design: from Audio to THz
Plenary Auditorium
Tuesday September 20, 2022 (14:20 - 15:00)
Chair: Andrea Baschirotto
While going through my research life I witness the history of CMOS analog design. I was lucky to be at U.C. Berkeley in the early eighties when all this started and my PhD with Prof. Paul Gray was part of it. The Berkeley microelectronics group was among the first to do pioneering research on this area. I maintained my focus on analog CMOS also when I moved to the University of Pavia even if the dominance of digital circuits and the dream of analog design automation decreased the interest on it. In the last 40 years CMOS circuits move from audio to THz applications as the technology scaled by almost three orders of magnitude (from 3 mm to 5 nm). This talk will go through this amazing evolution showing some examples of implemented circuit and system primarily for RF but also in other areas like disk drive or fiber optics interfaces. I will draw from academic as well as industry pointing out the role of device, circuit and architectural innovations toward this evolution. I hope this talk could be useful to bring motivation for younger researchers to drive the next CMOS developments.
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Rinaldo Castello (University of Pavia, IT)
Rinaldo Castello graduated from the University of Genova (summa cum laude) in 1977 and received the Ph. D. from the University of California, Berkeley, in ‘84. From ‘83 to ‘85 he was Visiting Assistant Professor at the University of California, Berkeley. In 1987 he joined the University of Pavia where he is now a Full Professor. He consulted for ST-Microelectronics, Milan, Italy up to 2005 in ‘98 he started a joint research centre between the University of Pavia and ST and was its Scientific Director up to ‘05. He promoted the establishing of several design centre from multinational IC companies around Pavia, among them Marvell for which he was a consultant from 2005 to 2016. More recently has establish a strong research partnership with Huawei. Rinaldo Castello has been a member of the TPC of the ESSCIRC since 1987 and of ISSCC from ‘92 to ‘04. He was Technical Chairman of ESSCIRC '91 and General Chairman of ESSCIRC ‘02, Associate Editor for Europe of the IEEE J. of Solid-State Circ. from '94 to '96 and Guest Editor of its July '92 special issue. From 2000 to 2007 he has been Distinguished Lecturer of the IEEE Solid State Circuit Society. Prof Castello was named one of the outstanding contributors for the first 50 and 60 years of ISSCC and a co-recipient of the Best Paper Award at the 2005 Symposium on VLSI of the Best Invited Paper Award at the 2011 CICC and of the Best Evening Panel Award at ISSCC 2012 and 2015. He was one of the two European representatives at the Plenary Distinguished Panel of ISSCC 2013 and the Summer 2014 Issue of the IEEE Solid State Circuit Magazine was devoted to him. Rinaldo Castello is a Fellow of the IEEE.
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From Less Batteries to Battery-Less: Enabling a Greener World through Ultra-Wide Power-Performance Adaptation via nWs and down to pWs
Plenary Auditorium
Wednesday September 21, 2022 (16:00 - 16:40)
Chair: Andrea Mazzanti
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Aggressive battery shrinkage and its ultimate elimination are crucial goals for our community, in view of the massive environmental and economic impact of their production, deployment, replacement and disposal for the next trillion of IoT devices. In self-powered systems, this goal mandates ultra-wide energy adaptation to handle the typically wide variability in power availability, performance target and incoming data temporal profile. Adaptation is a prerequisite to assure continuous operation despite the limited and widely fluctuating energy source (e.g., battery discharge, harvested power), swift response upon the occurrence of events of interest (e.g., on-chip data analytics), and extremely low consumption in the common case. These requirements have led to a decisive demand for a new breed of integrated systems having extremely wide energy/power scalability and adaptation, well beyond conventional voltage scaling or sub-threshold operation.
This keynote introduces innovative design principles for silicon systems that are always-on while not having any battery inside or other energy storage. Key ideas and silicon demonstrations are illustrated through virtual demos for the entire signal chain from sensing to computing, power management and wireless transceivers fitting existing infrastructure (e.g., WiFi). Power-scaling up to six orders of magnitude is shown to enable next-generation pervasive integrated systems with cost well below 1$, size of few millimeters, long lifetime well beyond the traditional shelf life of batteries, yet at near-100% up-time.
In this keynote, a clear pathway is ultimately defined to support sustainable growth of applications requiring large-scale deployments of silicon systems, making our planet smarter. And greener too.
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Massimo Alioto (National University of Singapore, SG)
Massimo Alioto is with the ECE Department of the National University of Singapore, where he leads the Green IC group, the Integrated Circuits and Embedded Systems area, and the FD-fAbrICS research center on intelligent&connected systems. Previously, he held positions at the University of Siena, Intel Labs – CRL (2013), University of Michigan - Ann Arbor (2011-2012), University of California – Berkeley (2009-2011), EPFL - Lausanne.
He is (co)author of 330 publications on journals and conference proceedings, and four books with Springer, such as the popular title “Enabling the Internet of Things – from Integrated Circuits to Integrated Systems”. His primary research interests include ultra-low power integrated systems, widely energy-scalable circuits, architectures and circuits for machine intelligence, and hardware security, among the others.
He is the Editor in Chief of the IEEE Transactions on VLSI Systems, and was Deputy Editor in Chief of the IEEE Journal on Emerging and Selected Topics in Circuits and Systems. Prof. Alioto was the Chair of the “VLSI Systems and Applications” Technical Committee of the IEEE CASS (2010-2012), Distinguished Lecturer (2009-2010, 2022-2023), members of the Board of Governors (2015-2020), and IEEE SSCS Distinguished Lecturer (2020-2021). He served as Guest Editor of numerous journal special issues, Technical Program Chair of IEEE conferences (e.g., ISCAS 2023, SOCC, ICECS), and TPC member (ISSCC, ASSCC). Prof. Alioto is an IEEE Fellow.
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Innovations for the Intelligent Edge
Plenary Auditorium
Thursday September 22, 2022 (10:10 - 10:50)
Chair: Joao Goes
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Massive amounts of data are and will continue to be generated when everything becomes intelligent and connected, and where data-driven decision making becomes a necessity. Data sources are also becoming increasingly distributed and mobile. These trends have resulted in the rise of the Intelligent Edge, where compute is brought closer to the data source to address scale and latency requirements. The opportunity is to leverage the emerging confluence of compute, communication, and AI at the Edge to wisely partition complex workloads between Edge and cloud, and to transform the way human and machines interact with the world. Consequently, industry and academia need to innovate faster than ever in key technologies to keep up with this rapidly evolving market. This talk will cover the required technology innovations and challenges in both 1) monolithic/heterogeneous integration on the technology side, as well as (2) design and architecture on the circuits/systems side, spanning both compute and connectivity domains for a digitized world where everything can be made intelligent and connected.
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Tanay Karnik (Intel, US)
Tanay Karnik is a Senior Principal Engineer and Director of Heterogeneous Platforms Lab of Intel Labs. Previously he was the Director of Intel's University Research Office. He received his Ph.D. in Computer Engineering from UIUC and joined Intel in 1995. His research interests are in the areas of heterogeneous integration, small form factor systems, 3D architectures, variation tolerance, power delivery and architectures for novel devices. He has published over 100 technical papers, has 125 issued and 41 pending patents in these areas. He received an Intel Achievement Award for the pioneering work on integrated power delivery. He has presented several keynotes, invited talks and tutorials, and has served on 7 PhD students' committees. He was a member of ISSCC, DAC, ICCAD, ICICDT, ISVLSI, ISCAS, 3DIC and ISQED program committees and JSSC, TCAD, TVLSI, TCAS review committees. Tanay was General Chair of ISLPED'14, ASQED’10, ISQED'09, ISQED'08 and ICICDT'08. Tanay is an IEEE Fellow, an ISQED Fellow, an Associate Editor for TVLSI, a Senior Advisory Board Member of JETCAS and a Guest Editor for JSSC.
